首頁 > 業內動態 > 海外情報 > DSP cores target 3G, VoIP

DSP cores target 3G, VoIP

52RD.com 2007年9月3日 EE Times            評論:1條 查看 我來說兩句
  

Fabless silicon intellectual-property vendor Ceva Inc. has introduced the Ceva-TeakLite-III family of DSP cores, targeting 2.5G and 2G cellular basebands, HD audio, VoIP and portable audio players. The first three family members, the TL3210, TL3211 and TL3214, are assembly-code-compatible with previous-generation TeakLite cores, but incorporate many enhancements.

Of particular interest to DSP developers is the addition of 32bit and dual 16 x 16bit multipliers. (The TeakLite I and II only have a single 16bit multiplier.) The 32bit multipliers offer the increased precision needed for high-fidelity audio applications, while the dual 16 x 16bit multipliers boost performance for a wide range of DSP applications.

The TeakLite-III also gets a speed boost from new audio-oriented instructions and instructions for accelerating FFT, Viterbi and Huffman algorithms. Initial performance estimates by Ceva show TeakLite-III cores to be 4x faster than previous TeakLite cores on basic operations and twice as fast on most popular audio codecs. The cores will operate at 350MHz in a 90nm process and up to 425MHz in a 65nm process. The company largely enabled the increase in clock speed by deepening the pipeline to 10 stages, up from four stages in previous TeakLite cores.

Migration to 32bits
Other changes include migration to32bit architecture (TeakLite I and II were 16bit architectures) and new RISC features. The RISC features include a 32bit general-purpose register bank, a 32bit linear address space that extends the addressable memory to 4Gbytes and a cached-memory subsystem that frees the developer from managing memory.

Branch prediction and conditional instructions improve the performance of decision-making code.

The TeakLite-III nominally uses 32bit instructions, but it also supports a comprehensive 16bit instruction set. An entire application can be written using only the 16bit instructions, or programmers can mix 16bit and 32bit instructions. That flexibility allows developers to make trade-offs between code size and performance.

Other instruction sets, such as the instructions for the ARM Thumb2 core, offer similar capabilities.

TeakLite III continues the trend in DSP cores of incorporating more control functionality. It will likely compete against other dual-MAC DSPs, such as Texas Instruments’ C55x+, which runs at 400-500MHz under worst-case conditions. It will also compete with 32bit RISC processors that incorporate DSP functionality, such as the ARM11 and MIPS24KEc cores.

Ceva reports that two top-tier semiconductor companies have licensed TeakLite III cores: a U.S.-based vendor developing a multimode baseband chip and an Asian vendor developing chips for HD audio applications.

The Ceva-TL3210 and TL3214 are available for licensing today. The TL3211 is slated for licensing in early 2008.

(52RD.com)
已有1位網友發表了看法 查看 我來說兩句
讀取...
相關報道
評 論
1樓 52RD網友 83.110.*.* 發表于 2012-8-8 03:50 回復
//喈曕喁嵿疅喈苦畷喁嵿畷喈む瘝喈む畷喁嵿畷, 喈む喁嵿疅喈苦畷喁嵿畷喈掂瘒喈`瘝喈熰喈?喈ㄠ喈曕喁嵿喁?4 喈氞喈編瘉喈喈瘓 喈喈側喈喁?喈掂喁嵿喁佮喁堗畷喁嵿畷喁?喈夃喁嵿喈距畷喁嵿畷喈苦 喈曕喈編喈む瘝喈む瘉喈?喈嗋畾喈苦喈苦喁堗畷喈赤瘝 喈庎喁嵿喁?喈夃畽喁嵿畷喈赤瘝 喈掂喈苦喁嵿喈熰 喈む喁堗喁嵿喁?喈掂瘓喈む瘝喈む喈班瘉喈曕瘝喈曕喈距喁? 喈撪喁? 喈呧喁?喈灌喈ㄠ瘝喈む瘉喈曕瘝喈曕喁佮畷喁嵿畷喁?喈疅喁嵿疅喁佮喁嵿喈距喈?//correctu.. for example, that airctle on a parpana gurukkal caught for same reason..as for the matter, andha relatives nenachadhu dhaan seri.. indha madhiri paedophilic b*******a (tamizhla sonnaa th*******) uyiroda koluthanum
共有評論1篇 查看所有評論
新聞導航 Navigation
精彩評論 Commentmore...
特別推薦 Recommend
北京pk10彩票玩法介绍